Logic Style Comparison for Ultra Low Power Applications
نویسندگان
چکیده
Power consumption factors such as leakage and device capacitance are inherently dependent on the type of logic family chosen to implement an application. This work compares the suitability of static CMOS, DPL, DVL, CPL and pseudo-nMOS logic families for use in near-threshold supply voltage environments. Through the joint analysis of addition logic and a register, we show a combination of CMOS and passgates performs best in terms of energy. The results of this analysis also demonstrate how the optimum supply voltage varies with logic styles in ultra low power systems.
منابع مشابه
Ultra Low Power Symmetric Pass Gate Adiabatic Logic with CNTFET for Secure IoT Applications
With the advent and development of the Internet of Things, new needs arose and more attention was paid to these needs. These needs include: low power consumption, low area consumption, low supply voltage, higher security and so on. Many solutions have been proposed to improve each one of these needs. In this paper, we try to reduce the power consumption and enhance the security by using SPGAL, ...
متن کاملStatic Differential Ultra Low-Voltage Domino CMOS logic for High Speed Applications
In this paper we present a novel static differential ultra low-voltage (ULV) CMOS logic style for High-Speed applications . The proposed logic style is aimed for high speed serial adders in ultra low-voltage applications. The differential ultra low-voltage inverter presented have less than 10% of the delay than standard CMOS inverters for supply voltages less than 500mV . The simulated data pre...
متن کاملDesigning of Full Adder Circuits for Low Power
Full adders are important components in applications such as digital signal processing (DSP) architecture, and microprocessors. Over the past decade, several adiabatic logic styles have been reported. This paper deals with the design of a 1-bit full adder using adiabatic logic style (DTGAL), which are derived from static CMOS logic, without a large change. This paper also proposes a new design ...
متن کاملUltra Low Power High Speed MAC Unit Using LP-HS Logic in CMOS Technologies
A modified approach for constant delay logic style is developed in this paper to provide improved power and delay named LP-HS logic. Constant delay logic style is examined against the LP-HS logic, by analysis through simulation. It is shown that the proposed LP-HS logic has low power, delay and power delay product over the existing constant delay logic style. Multiplier accumulator unit is one ...
متن کاملUltra-Low-Energy DSP Processor Design for Many-Core Parallel Applications
Background and Objectives: Digital signal processors are widely used in energy constrained applications in which battery lifetime is a critical concern. Accordingly, designing ultra-low-energy processors is a major concern. In this work and in the first step, we propose a sub-threshold DSP processor. Methods: As our baseline architecture, we use a modified version of an existing ultra-low-power...
متن کامل